Higher integration of semiconductor devices is required to satisfy consumer demands for superior performance and cost restrictions. Since integration is an important factor in determining product prices, increased integration is desired. In the case of two-dimensional or planar semiconductor devices, integration is mainly determined by the area occupied by a unit memory cell and, thus, integration is greatly influenced by the level of a fine pattern forming technology. However, expensive process equipment needed to increase pattern fineness sets a practical limitation on increasing integration for two-dimensional or planar semiconductor devices. To address these issues, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have been proposed.